PXA320 Dynamic Memory Controller Summary

1. SDRAM Configuration Register(MDCNFG)
The MDCNFG register contains control bits for configuring the SDRAM with parameters such as tRP, tRCD, tRAS, tRC. Both SDRAM chip selects must use the same parameters.

2. SDRAM Refresh Control Register(MDREFR)
The MDREFR register contains control bits for SDRAM refresh.

3. SDRAM Mode Register Set Configuration Register(MDMRS)
The MDMRS register is used to issue MRS and EMRS commands to SDRAM

4. DDR Hardware Calibration Register(DDR_HCAL)
This register allows hardware to calibrate and set the strobe delay lines.

5. DDR Write Strobe Calibration Register(DDR_WCAL)
This register lets hardware calibration set the write-strobe delay lines.

6. Dynamic Memory Controller Interrupt Enable Register(DMCIER)
The DMCIER is the Interrupt Enable register for all of the dynamic-memory controller interrupts.

7. Dynamic Memory Controller Interrupt Status Register(DMCISR)
The DMCISR is the Intrrrupt Status register for all of the dynamic-memory controller interrupts.

8. Delay Line Status Register(DDR_DLS)
The read-only Delay Line Status register monitors the delay-line values on strobes DQSx. DDR_DLS contains calibration information for controlling the external-bus delay lines and DQSx.

9. External Memory Pin Interface Control Register(EMPI)
The EMPI register controls the external-memory pin-interface(EMPI) module.

10. Rcomp Control Register(RCOMP)
The Rcomp Control register is similar in concept to the SDRAM Refresh Control register, MDREFR. Both registers use a counter clocked off of a 13-MHz clock to initiate events, and both registers contain an identical software mechanism for initiating their respective events.